LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY DECODE_TEST IS
END DECODE_TEST;
 
ARCHITECTURE behavior OF DECODE_TEST IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DECODE_UNIT
    PORT(
         clk : IN  std_logic;
         next_pc_in : IN  std_logic_vector(31 downto 0);
         next_instruction : IN  std_logic_vector(31 downto 0);
         wb_write_dst : IN  std_logic_vector(4 downto 0);
         wb_write_data : IN  std_logic_vector(31 downto 0);
         wb_write_en : IN  std_logic;
         invalid : OUT  std_logic;
         ALU_op : OUT  std_logic_vector(5 downto 0);
         ALU_src : OUT  std_logic;
         reg_dst : OUT  std_logic;
         branch : OUT  std_logic;
         mem_read : OUT  std_logic;
         mem_write : OUT  std_logic;
         mem_reg : OUT  std_logic;
         reg_write_en : OUT  std_logic;
         next_pc_out : OUT  std_logic_vector(31 downto 0);
         data_outp1 : OUT  std_logic_vector(31 downto 0);
         data_outp2 : OUT  std_logic_vector(31 downto 0);
         immediate_offset : OUT  std_logic_vector(31 downto 0);
         wb_dst1 : OUT  std_logic_vector(4 downto 0);
         wb_dst2 : OUT  std_logic_vector(4 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal next_pc_in : std_logic_vector(31 downto 0) := (others => '0');
   signal next_instruction : std_logic_vector(31 downto 0) := (others => '0');
   signal wb_write_dst : std_logic_vector(4 downto 0) := (others => '0');
   signal wb_write_data : std_logic_vector(31 downto 0) := (others => '0');
   signal wb_write_en : std_logic := '0';

 	--Outputs
   signal invalid : std_logic;
   signal ALU_op : std_logic_vector(5 downto 0);
   signal ALU_src : std_logic;
   signal reg_dst : std_logic;
   signal branch : std_logic;
   signal mem_read : std_logic;
   signal mem_write : std_logic;
   signal mem_reg : std_logic;
   signal reg_write_en : std_logic;
   signal next_pc_out : std_logic_vector(31 downto 0);
   signal data_outp1 : std_logic_vector(31 downto 0);
   signal data_outp2 : std_logic_vector(31 downto 0);
   signal immediate_offset : std_logic_vector(31 downto 0);
   signal wb_dst1 : std_logic_vector(4 downto 0);
   signal wb_dst2 : std_logic_vector(4 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DECODE_UNIT PORT MAP (
          clk => clk,
          next_pc_in => next_pc_in,
          next_instruction => next_instruction,
          wb_write_dst => wb_write_dst,
          wb_write_data => wb_write_data,
          wb_write_en => wb_write_en,
          invalid => invalid,
          ALU_op => ALU_op,
          ALU_src => ALU_src,
          reg_dst => reg_dst,
          branch => branch,
          mem_read => mem_read,
          mem_write => mem_write,
          mem_reg => mem_reg,
          reg_write_en => reg_write_en,
          next_pc_out => next_pc_out,
          data_outp1 => data_outp1,
          data_outp2 => data_outp2,
          immediate_offset => immediate_offset,
          wb_dst1 => wb_dst1,
          wb_dst2 => wb_dst2
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
